PHiLIP
port.h
1 /*
2  * Copyright 2020 Kevin Weiss for HAW Hamburg
3  *
4  * This file is subject to the terms and conditions of the MIT License. See the
5  * file LICENSE in the top level directory for more details.
6  * SPDX-License-Identifier: MIT
7  */
8 
9 /*
10  ******************************************************************************
11  * @file port.h
12  * @author Kevin Weiss
13  * @date 20.03.2019
14  * @brief Board/cpu specific porting.
15  ******************************************************************************
16  */
17 
18 #ifndef PORT_H_
19 #define PORT_H_
20 
21 #ifdef BLUEPILL
22 #include "port_bluepill.h"
23 #endif
24 
25 #ifdef NUCLEOF103RB
26 #include "port_nucleo_f103rb.h"
27 #endif
28 
29 /******************************************************************************/
30 /* <TEMPLATE defines> *********************************************************/
31 /******************************************************************************/
32 /*
33  * <MODULE>_INST
34  *
35  * <MODULE>_CLK_EN
36  * <MODULE>_CLK_DIS
37  * <MODULE>_GPIO_CLK_EN
38  *
39  * <MODULE>_GPIO_AF_REMAP
40  *
41  * <MODULE>_INT
42  * <MODULE>_IRQ
43  *
44  * <MODULE>_DMA_INST
45  * <MODULE>_DMA_INT
46  * <MODULE>_DMA_IRQ
47  */
48 
49 /******************************************************************************/
50 /* Pin and ports defines ******************************************************/
51 /******************************************************************************/
52 #define LED0 LED0_GPIO_Port, LED0_Pin
53 
54 #define DEBUG0 DEBUG0_GPIO_Port, DEBUG0_Pin
55 #define DEBUG1 DEBUG1_GPIO_Port, DEBUG1_Pin
56 #define DEBUG2 DEBUG2_GPIO_Port, DEBUG2_Pin
57 
58 #define TEST_PASS TEST_PASS_GPIO_Port, TEST_PASS_Pin
59 #define TEST_WARN TEST_WARN_GPIO_Port, TEST_WARN_Pin
60 #define TEST_FAIL TEST_FAIL_GPIO_Port, TEST_FAIL_Pin
61 
62 #define USER_BTN USER_BTN_GPIO_Port, USER_BTN_Pin
63 #define DUT_RST DUT_RST_GPIO_Port, DUT_RST_Pin
64 
65 #define DUT_ADC DUT_ADC_GPIO_Port, DUT_ADC_Pin
66 
67 #define PM_LO_ADC PM_LO_ADC_GPIO_Port, PM_LO_ADC_Pin
68 #define PM_HI_ADC PM_HI_ADC_GPIO_Port, PM_HI_ADC_Pin
69 #define PM_V_ADC PM_V_ADC_GPIO_Port, PM_V_ADC_Pin
70 
71 #define DUT_TX DUT_TX_GPIO_Port, DUT_TX_Pin
72 #define DUT_RX DUT_RX_GPIO_Port, DUT_RX_Pin
73 #define DUT_CTS DUT_CTS_GPIO_Port, DUT_CTS_Pin
74 #define DUT_RTS DUT_RTS_GPIO_Port, DUT_RTS_Pin
75 
76 #define DUT_IC DUT_IC_GPIO_Port, DUT_IC_Pin
77 
78 #define IF_TX IF_TX_GPIO_Port, IF_TX_Pin
79 #define IF_RX IF_RX_GPIO_Port, IF_RX_Pin
80 
81 #define DUT_NSS DUT_NSS_GPIO_Port, DUT_NSS_Pin
82 #define DUT_SCK DUT_SCK_GPIO_Port, DUT_SCK_Pin
83 #define DUT_MISO DUT_MISO_GPIO_Port, DUT_MISO_Pin
84 #define DUT_MOSI DUT_MOSI_GPIO_Port, DUT_MOSI_Pin
85 
86 #define DUT_SCL DUT_SCL_GPIO_Port, DUT_SCL_Pin
87 #define DUT_SDA DUT_SDA_GPIO_Port, DUT_SDA_Pin
88 
89 #define DUT_PWM DUT_PWM_GPIO_Port, DUT_PWM_Pin
90 #define DUT_DAC DUT_DAC_GPIO_Port, DUT_DAC_Pin
91 
92 /******************************************************************************/
93 /* CPU Macros *****************************************************************/
94 /******************************************************************************/
95 #define DUT_IC_REMAINING_BUF(x) (x.Instance->CNDTR)
96 #define DUT_IC_OV_OCCURED(x) (x->Instance->SR & TIM_SR_UIF)
97 #define DUT_IC_OV_CLEAR(x) x->Instance->SR &= ~(TIM_SR_UIF)
98 
99 #define ADC_DATA_READY(x) (x.Instance->SR & ADC_FLAG_EOC)
100 
101 #define DEFAULT_INT_PRIO 1
102 
103 /******************************************************************************/
104 void init_periphs(void);
105 void init_clock(void);
106 void _Error_Handler(char *file, int line);
107 
108 #endif /* PORT_H_ */
_Error_Handler
void _Error_Handler(char *, int)
This function is executed in case of error occurrence.
Definition: port.c:232